Behavioral-Level Synthesis of Heterogeneous BISR Reconfigurable ASICs1

Behavioral-level synthesis techniques have traditionally focussed on design of a fully-hardwired application-specific implementation of a given computation. In this paper, new techniques are presented for the synthesis of reconfigurable hardware. The technique is applicable for synthesis of several classes of designs, including: 1) design for fault tolerance against permanent faults, 2) design for improved manufacturability, and 3) design of Application Specific Programmable Processors (ASPPs) — processors designed to perform any computation from a specified set on a single implementation platform. This paper focuses on design techniques for efficient Built-InSelf-Repair (BISR), and thus directly addresses the former two applications. Previous BISR techniques have been based on replacing a failed module with a backup of the same type. We present new heterogeneous BISR methodologies which remove this constraint and enable replacement of a module with a spare of a different type. The approach is based on the flexibility of behavioral-level synthesis to explore the design space. Two behavioral synthesis techniques are developed; the first method is through assignment and scheduling, and the second utilizes transformations. Experimental results verify the effectiveness of the approaches. In particular, significant yield and productivity improvements, calculated using state-of-the art yield modeling techniques, show the power of these techniques for improving manufacturability. 1. Preliminary versions of this work appeared in the Proc. IEEE/ACM ICCAD, November 1993 and in the 1993 Proc. of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 1993.